1. Field of the Invention
The invention relates to information processing technologies, and more particularly to an information processing apparatus for reading a plurality of read units of data from a memory and generating a data stream, an information processing method using the apparatus, and a data stream generation method.
2. Description of the Related Art
With the recent remarkable advance of computer graphic technologies and image processing technologies for use in the fields of computer games, digital broadcasting, etc., capabilities for processing data of greater sizes at higher speed are required of information processing apparatuses such as a computer, a game console, and a television set. In order for these information processing apparatuses to achieve sophisticate arithmetic processing, it is effective to improve the processing speed of a processor itself or provide a plurality of processors for parallel processing.
When processors improve in operating speed through such technological development as enhanced operating clocks and multi-processor configuration as described above, a problem of memory access time comes to the surface. One of measures for reducing the access time is to constitute a hierarchical memory system through the introduction of cache memories. Cache memories are auxiliary memories of high speed and small capacities, which copy and store part of data stored in a main memory. In the cases of task processing with uneven data accesses, data to be accessed repeatedly can be stored into cache memories for reduced access time.
Whereas the introduction of cache memories reduces the memory access time, demands for faster information processing apparatuses are increasing day by day. A further reduction in the access time is thus desired. For example, in cache systems, applications having low cache hit rates naturally increase the frequency of accesses to the main memory, thereby making it difficult to obtain performance desired of the information processing apparatuses. In view of manufacturing cost and ease of implementation, however, other improvements for reducing cache-miss penalties by such means as accelerating the main memory, increasing the capacities of the cache memories, and extending the bus bandwidth have limitations in practice.